Recently, Silicon Oxide Nitride Oxide Silicon (SONOS) devices have been recognized as important non-volatile memory devices. In particular, a SONOS flash memory cell based on two transistors (Tr) is a stable flash memory device due to its effective prevention of over-erases. In spite of this advantage, a two transistor SONOS flash memory has the disadvantage of a relatively large cell size, which undermines miniaturization.
FIG. 1 is a sectional view schematically showing an EEPROM device.
Referring to FIG. 1, after an isolation region is formed in a semiconductor substrate 10, a well process, a photo process and an ion implantation process for adjusting the threshold voltage Vth of a cell are performed. Thereafter, an Oxide-Nitride-Oxide (ONO) layer 20 composed of oxide layer 21, nitride layer 23, and oxide layer 25 is formed over the semiconductor substrate 10. Next, a photo process and an etching process for patterning the ONO layer 20 are performed. Subsequently, an oxidation process for forming a gate oxide layer 30 is performed.
The gate layer is formed and is patterned using a photo process and an etching process to form a first gate 41 and a second gate 42. Next, a dopant ion implantation process for forming junctions 50, such as source/drain junctions 51 and an intermediate transfer node junction 53, is performed.
Thereafter, a dielectric layer 60 and a contact 65 penetrating through the dielectric layer 60 are formed, and a bit line 70 may be formed.
However, such a cell structure based on two transistors is accompanied by an increase in the cell area due to the intermediate transfer node junction 53. That is, the first gate 41 which is an access gate, and the second gate 42 which is a cell gate, are separately arranged in a plane, thereby increasing the cell area due to such a planar structure. Therefore, it is difficult to reduce the cell area using this method.